1. Field of Invention
The present invention relates to a display panel system, and more particular to a display panel system with low power consumption multiplexers.
2. Description of Related Art
Rapid development within the fields of information and communication has caused an increase in the demand for thin, lightweight and low cost display devices for viewing information. Industries that develop displays are responding to these needs by placing high emphasis on developing flat panel type displays.
Historically, Cathode Ray Tube (CRT) monitors have been widely used as a display device in applications such as televisions, computer monitors, and the like, because CRT monitors can display under high luminance. However, the CRT monitors cannot adequately satisfy present demands for display applications that require reduced volume and weight, portability, and low power consumption, while having a large screen size and high resolution. Out of this need, the display industry has placed high emphasis on developing flat panel displays to replace the CRT monitors. Over the years, flat panel displays have found wide use in monitors for computers, spacecraft, and aircraft. Examples of flat panel display types currently used include the LCD, the electroluminescent display (ELD), the field emission display (FED), and the plasma display panel (PDP).
Characteristics required for an ideal flat panel display include a lightweight, high luminance, high efficiency, high resolution, high speed response time, low driving voltage, low power consumption, low cost, and natural color.
Development and application of thin film transistor (TFT)-LCD industries have been accelerated in accordance with the increase in the dimensions and increase in the resolution. Many efforts have been made to lower power consumption of the LCD display system.
FIG. 1 shows a simplified block diagram of a display panel system. For example, the display panel is a liquid crystal display (LCD) panel. The display panel system at least includes a display panel 10 and a source driver 15. The display panel 10 at least includes a multiplexer stage 13. The resolution of the display panel 10 is, for example, 320 columns*240 rows. The source driver 15 drives LCD cells on the display panel 10.
FIG. 2 shows a part of the multiplexer stage 13 of FIG. 1. For simplicity, in FIG. 2, only the n-th row (n) is shown. As known, an individual pixel includes three sub-pixels R/G/B. Symbols “R1”, “B1”, “G1” refer to the three sub-pixels in the first pixel in row(n), “R2”, “B2”, “G2” refer to the three sub-pixels in the second pixel in row(n) and so on. Signals S(n, 1), S(n, 2), S(n, 3), S(n, 4) and S(n, 5) refer to source output signals from the source driver 15, wherein signal S(n, 1) is coupled to the sub-pixels R1/G1/B1 in the first row(n) via a multiplexer MUX (n, 1), and so on. Each multiplexer includes three transistors. For example, the multiplexer MUX (n, 1) includes transistors Tn,1, Tn,2 and Tn,3; the multiplexer MUX (n, 2) includes transistors Tn,4, Tn,5 and Tn,6 . . . and so on.
Control signals CKH1, CKH2 and CKH3 control on/off states of the transistors in the multiplexer stage 13. The waveforms of the control signals CKH1, CKH2 and CKH3 are shown in the bottom of FIG. 2. When the control signal CKH1 is logic H, the first transistor in each multiplexer is on and accordingly source output signals S(n, 1), S(n, 2), S(n, 3), S(n, 4) and S(n, 5) are directed (or written) into sub-pixels R1, R2, R3 . . . via the ON transistors Tn,1, Tn,4 . . . . Similarly, When the control signal CKH2 is logic H, the second transistor in each multiplexer is on and accordingly source output signals S(n, 1), S(n, 2), S(n, 3), S(n, 4) and S(n, 5) are directed (or written) into sub-pixels G1, G2, G3 . . . via the ON transistors Tn,2, Tn,5 . . . . When the control signal CKH3 is logic H, the third transistor in each multiplexer is on and accordingly source output signals S(n, 1), S(n, 2), S(n, 3), S(n, 4) and S(n, 5) are directed (or written) into sub-pixels B1, B2, B3 . . . via the ON transistors Tn,3, Tn,6 . . . .
The LCD panel display system has four driving modes, i.e., a frame inversion mode, a row inversion mode, a column inversion mode and a dot inversion mode. FIGS. 3a˜3d show the polarity of the source output signals and accordingly the sub-pixels in three consecutive frames under the four driving modes, respectively. Under the four driving modes, every time a frame is changed, the polarity of sub-pixels is changed from positive (+) to negative (−) or from negative (−) to positive (+). In FIGS. 3a˜3d, only three consecutive frames are shown.
As shown in FIG. 3a, in the frame inversion mode, the polarity of all sub-pixels in the panel is the same, either positive or negative. If the polarity of all sub-pixels is positive in the first frame, then changed into negative in the second frame, and then changed into positive in the third frame.
As shown in FIG. 3b, in the row inversion mode, the polarity of all sub-pixels in the same row is the same (either positive or negative) but is inverted in the next row. For example, in the first frame, the polarity of all sub-pixels in row 1 is positive and the polarity of all sub-pixels in row 2 is negative. When the frame is changed into the second frame, the polarity of all sub-pixels in row 1 is inverted into negative and the polarity of all sub-pixels in row 2 is inverted into positive. When the frame is changed into the third frame, the polarity of all sub-pixels in row 1 is inverted into positive and the polarity of all sub-pixels in row 2 is inverted into negative.
As shown in FIG. 3c, in the column inversion mode, the polarity of all sub-pixels in the same column single row is all the same (either positive or negative) but is inverted in the next column. For example, in the first frame, the polarity of all red sub-pixels R1 in the first column are positive, the polarity of all green sub-pixels G1 in the second column are negative, and the polarity of all blue sub-pixels B1 in the third column are positive. When the frame is changed into the second frame and then the third frame, the polarity of all red sub-pixels R1 in the first column is inverted into negative and then positive, the polarity of all green sub-pixels G1 in the second column is inverted into positive and then negative, and the polarity of all blue sub-pixels B1 in the third column is inverted into negative and then positive.
As shown in FIG. 3d, in the dot inversion mode, the polarity of any adjacent sub-pixels is different from each other. For example, in the first frame, the polarity of the red sub-pixels R1 in row (1) is positive, but the polarity of its adjacent sub-pixels, the green sub-pixels G1 in row (1) and the polarity of the red sub-pixels R1 in row (2) is both negative. When the frame is changed into the second frame and then the third frame, the polarity of the red sub-pixels R1 in row (1) is inverted into negative and then positive, and the polarity of its adjacent sub-pixels, the green sub-pixels G1 in row (1) and the polarity of the red sub-pixels R1 in row (2) is both inverted into positive and then negative.
For reducing power consumption, the connections between the source output signals and the sub-pixels had better to be optimized. But, in prior art, the connections are not optimized, so the power consumption due to voltage swing and frequency of the source output signals is large, which increase overall power consumption of the display panel system.
FIGS. 4a˜4d show the source output signals of row(n) and row(n+1) under these four driving modes, when the display panel shows a cyan screen. To show a cyan screen, the red sub-pixels are driven high and the green/blue sub-pixels are driven low. In FIGS. 4a˜4d, arrows refer to large voltage swing. Usually, large voltage swing and high swing frequency result in large power consumption. For example, in FIG. 4a, because the red sub-pixel R1 is driven positive high and the green sub-pixel G1 is driven positive low, a large voltage swing occurs when the source output signals S(n,1) is changed from positive high to positive low. Furthermore, in the prior art, voltage swing frequency under these four driving modes are high, and accordingly, power consumption of the prior multiplexer is high.
Therefore, a low power consumption multiplexer configuration, which reduced voltage swing rates (signal change rates) is needed for power saving.